1. Field of the Invention
The present invention relates to a digital circuit which operates in synchronism with a digital signal, and more particularly to a semiconductor device having a single or a plurality of the digital circuits and a driving method thereof.
2. Description of the Related Art
A logic circuit processing a digital signal (hereinafter referred to as a digital circuit) is configured with a single or a plurality of logic elements as a basic unit. The logic element is a circuit which provides one output corresponding to a single or a plurality of inputs. Examples of the logic elements include an inverter, an AND, an OR, a NOT, a NAND, a NOR, a clocked inverter, and a transmission gate and the like.
The logic element is configured with a single or a plurality of circuit elements such as transistors, resistors and capacitor elements. By operating the plurality of circuit elements in accordance with a digital signal inputted to the logic element, a signal potential or a current which is to be supplied to a subsequent circuit is controlled. Note that, in this specification, connection means an electrical connection unless otherwise stated. Therefore, in the configurations of the invention, elements which enable the electrical connections (other elements or switches or the like) may be interposed among the predetermined connections additionally.
Given as an example herein is an inverter as one of the logic elements. A configuration and operation thereof are explained concretely below.
A circuit diagram of a general inverter is shown in FIG. 16A. In FIG. 16A, IN means an inputted signal (input signal), and OUT means an outputted signal (output signal). Meanwhile, VDD and VSS mean power source potentials and VDD is higher than VSS (VDD>VSS).
The inverter as shown in FIG. 16A includes a p-channel type TFT (Thin Film Transistor) 1301 and an n-channel type TFT 1302. A gate (G) of the p-channel type TFT 1301 and a gate of the n-channel type TFT 1302 are connected to each other, and the input signal IN is inputted to both gates. A first terminal of the p-channel type TFT 1301 receives VDD, and a first terminal of the n-channel type TFT 1302 receives VSS. Meanwhile, a second terminal of the p-channel type TFT 1301 and a second terminal of the n-channel type TFT 1302 are connected to each other and the output signal OUT is outputted from these second terminals to a subsequent circuit.
Note that, either of the first terminal or the second terminal corresponds to a source and the other corresponds to a drain. In the case of a p-channel type TFT, a terminal having a higher potential is a source and a terminal having a lower potential is a drain, and in the case of an n-channel type TFT, a terminal having a higher potential is a drain and a terminal having a lower potential is a source. Therefore, the first terminals of both TFTs correspond to sources (S) and the second terminals thereof correspond to drains (D) in FIG. 16A.
Generally, for an input signal, a digital signal having binary potentials is utilized. Two circuit elements of the inverter are operated in accordance with a potential of the input signal IN, thereby controlling a potential of the output signal OUT.
Next, an operation of the inverter as shown in FIG. 16A is explained with reference to FIGS. 16B and 16C. Note that in the FIGS. 16B and 16C, each circuit element is shown simply as a switch for clarification of the operating state.
FIG. 16B shows an operating state of each circuit element in the case where the input signal IN has a potential on the high potential side. Here, the potential on the high potential side of the input signal IN is referred to as VDD′ (VDD′≧VDD), and it is assumed to simplify the explanation, that a threshold voltage of the n-channel type TFT 1302 (VTHn) is equal or higher than 0 (VTHn≧0) and a threshold voltage of the p-channel type TFT 1301 (VTHp) is equal or lower than 0 (VTHp≦50).
When the gate of the p-channel type TFT 1301 receives the potential VDD′, a voltage between the gate and source (hereinafter referred to as a gate voltage) becomes VGS≧0 because VDD′≧VDD and the p-channel type TFT 1301 is thus turned OFF. Note that the gate voltage corresponds to a voltage obtained by subtracting a source potential from a gate potential.
Meanwhile, when the gate of the n-channel type TFT 1302 receives the potential VDD′ the gate voltage becomes VGS>0 because VDD′>VSS and the n-channel type TFT 1302 is thus turned ON. Therefore, the power source potential VSS is supplied to the subsequent circuit as a potential of the output signal OUT.
Next, an operating state of each circuit element in the case where the input signal IN has a potential on the low potential side is shown in FIG. 16C. Here, the potential on the low potential side of the input signal IN is referred to as VSS′ (VSS′≦VSS) and it is assumed to simplify the explanation, that a threshold voltage of the n-channel type TFT 1302 (VTHn) is equal or higher than 0 (VTHn≧0) and a threshold voltage of the p-channel type TFT 1301 (VTHp) is equal or lower than 0 (VTHp≦0).
When the gate of the n-channel type TFT 1302 receives the potential VSS′, the gate voltage becomes VGS≦0 because VSS′ is equal or lower than VSS (VSS′≦VSS) and the n-channel type TFT 1302 is thus turned OFF.
Meanwhile, when the gate of the p-channel type TFT 1301 receives the potential VSS′, the gate voltage becomes VGS is lower than 0 (VGS<0) because VSS′ is lower than VDD (VSS′<VDD) and the p-channel type TFT 1301 is thus turned ON. Therefore, the power source potential VDD is supplied to the subsequent circuit as a potential of the output signal OUT.
In this manner, each circuit element is operated in accordance with the potential of the input signal IN, thereby controlling the potential of the output signal OUT.
The operations of the inverter explained referring to FIGS. 16B and 16C are ones in the case where the binary potentials of the input signals IN (VDD′ and VSS′) are assumed to be VDD′≧VDD and VSS′≦VSS respectively. Hereinafter verified are operations of the inverter as shown in FIG. 16A in the case where it is assumed that VDD′ is lower than VDD (VDD′<VDD) and VSS′ is higher than VSS (VSS′>VSS). Note that VSS′<VDD′ is established.
First, FIG. 17A shows an operating state of each circuit element in the case where the input signal IN has a potential on the high potential side VDD′ (VDD′<VDD). Here, it is assumed to simplify the explanation, that a threshold voltage of the n-channel type TFT 1302 (VTHn) is equal or higher than 0 (VTHn≧0) and a threshold voltage of the p-channel type TFT 1301 (VTHp) is equal or lower than 0 (VTHp≦0).
When the gate of the p-channel type TFT 1301 receives the potential VDD′, the gate voltage becomes VGS<0 because VDD′<VDD is established. Therefore, when |VGS|>|VTHp|, the p-channel type TFT 1301 is turned ON. Meanwhile, when the gate of the n-channel type TFT 1302 receives the potential VDD′, the gate voltage becomes VGS>0 because VDD′ is higher than VSS (VDD′>VSS), thus the n-channel type TFT 1302 is turned ON.
Therefore, both p-channel type TFT 1301 and the n-channel type TFT 1302 are turned ON depending on the values of VDD, VDD′ and VTHp. That is, unlike the case as shown in FIG. 16B, a potential of the output signal OUT does not become VSS even when an input signal IN has a potential on the high potential side.
A potential of the output signal OUT is determined by the current flowing in each transistor. In FIG. 17A, when VGS of the n-channel type transistor TFT 1302 is referred to as VGSn and VGS of the p-channel type TFT 1301 is referred to as VGSp, |VGSn| is larger than |VGSp| (|VGSn|>|VGSp|). Therefore, the potential of the output signal OUT approaches closer to VSS than VDD when there is almost no difference between each transistor as to the characteristics and a ratio of a channel width W to a channel length L. However, the potential of the output signal OUT can approach closer to VDD than VSS depending on a mobility, a threshold voltage and the ratio of the channel width W to the channel length L of each TFT. In this case, the digital circuit does not operate normally, leading to a high possibility of malfunction. Further, it can cause a sequential malfunction in the subsequent digital circuit.
FIG. 17B shows an operating state of each circuit element in the case where the input signal IN has a potential on the low potential side VSS′ (VSS′>VSS). It is assumed to simplify the explanation, that a threshold voltage of the n-channel type TFT 1302 (VTHn) is equal or higher than 0 (VTHn≧0) and a threshold voltage of the p-channel type TFT 1301 (VTHp) is equal or lower than 0 (VTHp≦0).
When the gate of the n-channel type TFT 1302 receives the potential VSS′, the gate voltage becomes VGS<0 because VSS′ is higher than VSS (VSS′>VSS). Therefore, when |VGS|>|VTHn|, the n-channel type TFT 1302 is turned ON. Meanwhile, when a gate of the p-channel type TFT 1301 receives the potential VSS′, the gate voltage becomes VGS<0 because VSS′ is lower than VDD (VSS′<VDD), thus the p-channel type TFT 1301 is turned ON.
Therefore, the p-channel type TFT 1301 and the n-channel type TFT 1302 are both turned ON depending on the values of VSS, VSS′ and VTHn. That means, unlike the case as shown in FIG. 16C, a potential of the output signal OUT does not become VDD even when an input signal IN has a potential on the low potential side.
A potential of the output signal OUT is determined by a current flowing in each transistor. In FIG. 17B, |VGSn|<|VGSp|. Therefore, the potential of the output signal OUT approaches closer to VDD than VSS when there is almost no difference between each transistor as to the characteristics and ratio of channel width W to channel length L. However, the potential of the output signal OUT can approach closer to VSS than VDD depending on the mobility, threshold voltage and ratio of the channel width W to the channel length L of each TFT. In this case, the digital circuit does not operate normally, leading to a high possibility of a malfunction. Further, it can cause a sequential malfunction at a subsequent digital circuit.
As described above, in the inverter as shown in FIG. 16A, an output signal OUT having a desired potential is obtained when the binary potentials VDD′ and VSS′ of the input signal IN are in the relations of VDD′≧VDD and VSS′≦VSS respectively, thereby a normal operation is obtained. However, when the binary potentials VDD′ and VSS′ of the input signal IN are in the relations of VDD′<VDD and VSS′>VSS respectively, the output signal OUT having a desired potential is not obtained, thereby the inverter may not operate normally.
The above case is not exclusively limited to the inverter, but can be applied to other digital circuits. That is, when the binary potential of the input signal IN is out of the predetermined range, the circuit elements of the digital circuit malfunction. Therefore, the output signal OUT having a desired potential can not be obtained and the digital circuit does not function normally.
A potential of the input signal supplied from a circuit or a wiring of a prior stage is not always an appropriate value for operating the digital circuit normally. In this case, by adjusting the potential of the input signal by a level shifter, the digital circuit can operate normally. However, a high-speed operation of the semiconductor device is frequently hindered by using the level shifter, because level shifters generally have disadvantages in that the speed of rising and dropping of the potential of the output signal is slow as each of the circuit elements operate in conjunction with such that one circuit element triggers the operations of other circuit elements.
It is also difficult to obtain a high-speed operation because TFTs are not readily turned ON when a power source voltage is low whereby current is also reduced. Meanwhile, the power consumption increases when a power source voltage is increased to obtain a high-speed operation.
Further, current consumption increases since the n-channel type TFT 1302 and the p-channel type TFT 1302 are simultaneously turned ON and a short-circuit current flows in the TFTs.
To solve the foregoing problems, it is suggested that in a level shifter circuit having a first input inverter and a second output inverter, a DC level of a signal inputted to the second inverter from the first inverter is converted by capacitors (capacitor elements) and a bias means (Reference to Patent Document 1). However, in this circuit, a DC level conversion capacitor is connected between a gate of each transistor configuring the second inverter and an output terminal of the first inverter connected to a High-level power source potential or a Low-level power source potential at all times by the bias means. Therefore, the charge and discharge of these capacitors have damaging influence on the dynamic characteristics of the circuit (namely, causes the decrease in operation speed of the circuit), or the power consumption with the charge and discharge of the capacitors is increased to a considerable extent. Meanwhile, when there are fluctuations in threshold voltages of the transistors, it is difficult to match electrostatic capacitance of each capacitor to the corresponding transistors. Therefore, voltages of both terminals of the DC level conversion capacitor do not match the threshold voltages of the corresponding transistors, thus ON/OFF operation of the transistors may not be performed normally.
[Patent Document 1] Japanese Patent Laid-Open No. Hei 09-172367